1. Field of the Invention
This invention relates generally to non-volatile memory devices such as Flash EEPROM cells useful in memory arrays and programmable logic devices (PLDs). More particularly, it relates to an improved EEPROM cell structure and a method for fabricating such EEPROM cell structure so as to improve data retention.
2. Description of the Prior Art
As is generally well-known, an EEPROM cell utilizes a thin tunnel dielectric for electrically erasing and programming the cell. Typically, these EEPROM cells are formed by a plurality of floating gate MOS transistors disposed on a substrate in an integrated circuit. Each of the floating gate MOS transistors includes a pair of source/drain regions formed on a surface of a silicon substrate, a gate oxide film formed on the substrate between the source/drain regions, a thin tunneling dielectric area on the drain region, and a floating gate formed over the gate oxide film, and a stacked control gate disposed over the floating gate.
One of the major concerns is the data retention capability in operating an EEPROM cell based programmable logic device (PLD). As used herein, the term "data retention" is defined to be the length of time a particular EEPROM cell can retain information stored in the form of charges on the floating gate. When electrons traverse the tunnel oxide with no applied gate voltage to the cell, there is created a "low voltage leakage current." This small amount of current leakage will eventually cause a total discharge of the cell. Thus, it is generally desirable to reduce or eliminate the low voltage leakage current.
The low voltage leakage current is dependent upon the quality of the oxide layer. The conventional EEPROM cell uses a single layer of silicon dioxide (SiO.sub.2) as the tunneling dielectric whose quality is a function of the amount of charge that can be passed through the dielectric before breakdown of the floating gate occurs. Further, in view of the deep-submicron CMOS technology the device dimensions are being made smaller and smaller. As a result, the oxide layer thickness must be likewise reduced down so as to provide optimal device performance. However, this reduction of the oxide thickness causes its quality to be degraded thereby increasing the leakage current in the cell and reducing its data retention capability.
There have been attempts made heretofore in the prior art of using dielectrics with a dielectric constant "k" that is higher than the silicon dioxide (SiO.sub.2) in the MOS transistors as the gate dielectrics and in DRAM cells as the capacitor dielectrics for suppression of leakage current through the dielectric. These types of dielectrics are sometimes referred to as "high-k" dielectrics. Nevertheless, there still exists a need for an EEPROM cell structure and a method for fabricating the same so as to improve data retention.
The EEPROM cell structure of the present invention represents a significant improvement over the traditional EEPROM cell based PLD as previously described. This is achieved in the present invention through the use of a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barriers so as to suppress leakage current.